1. Field of the Invention
This invention relates generally to analog-to-digital converter (ADC) design and, more particularly, to the design of a time continuous pipeline ADC.
2. Description of the Related Art
Scientists and engineers often use measurement systems to perform a variety of functions, including measurement of a physical phenomena or unit under test (UUT), test and analysis of physical phenomena, process monitoring and control, control of mechanical or electrical machinery, data logging, laboratory research, and analytical chemistry, to name a few examples.
A typical measurement system comprises a computer system, which commonly features a measurement device, or measurement hardware. The measurement device may be a computer-based instrument, a data acquisition device or board, a programmable logic device (PLD), an actuator, or other type of device for acquiring or generating data. The measurement device may be a card or board plugged into one of the I/O slots of the computer system, or a card or board plugged into a chassis, or an external device. For example, in a common measurement system configuration, the measurement hardware is coupled to the computer system through a PCI bus, PXI (PCI extensions for Instrumentation) bus, a GPIB (General-Purpose Interface Bus), a VXI (VME extensions for Instrumentation) bus, a serial port, parallel port, or Ethernet port of the computer system. Optionally, the measurement system includes signal-conditioning devices, which receive field signals and condition the signals to be acquired.
A measurement system may typically include transducers, sensors, or other detecting means for providing “field” electrical signals representing a process, physical phenomena, equipment being monitored or measured, etc. The field signals are provided to the measurement hardware. In addition, a measurement system may also typically include actuators for generating output signals for stimulating a UUT.
Measurement systems, which may also be generally referred to as data acquisition systems, may include the process of converting a physical phenomenon (such as temperature or pressure) into an electrical signal and measuring the signal in order to extract information. PC-based measurement and data acquisition (DAQ) systems and plug-in boards are used in a wide range of applications in the laboratory, in the field, and on the manufacturing plant floor, among others.
Typically, in a measurement or data acquisition process, analog signals are received by a digitizer, which may reside in a DAQ device or instrumentation device. The analog signals may be received from a sensor, converted to digital data (possibly after being conditioned) by an Analog-to-Digital Converter (ADC), and transmitted to a computer system for storage and/or analysis. Then, the computer system may generate digital signals that are provided to one or more Digital-to-Analog converters (DACs) in the DAQ device. The DACs may convert the digital signal to an output analog signal that is used, e.g., to stimulate a UUT.
Many DAQ devices require ADCs having a topology that can be used for high-resolution conversion at fast rates (typically from 10 Ms/S [millions of samples per second] and beyond). One such topology is the widely used Sampled Pipeline Subranging Converter (SPSC). The SPSC ADC architecture is predominant in most applications that require sampling rates of greater than 5 Ms/S to 10 Ms/S. The SPSC architecture lends itself to a variety of relatively low cost IC processes—CMOS (complementary metal-oxide semiconductor) and BiCMOS (bi-polar CMOS) being the most popular among them. Current technology generally yields 12- to 16-bit resolution at sampling rates greater than 100 Ms/S.
FIG. 1 shows one example of an SPSC topology 100, as designed by Analog Devices. The pipelined architecture shown in FIG. 1 is a digitally corrected SPSC in which each stage operates on the data for one-half the sampling clock cycle, then passes its residue output to the next stage in the pipeline, prior to the next half clock cycle. The inter-stage track-and-hold (T/H) element (102, 110, etc.) serves as an analog delay line—timing is set such that it enters the hold mode when the first stage conversion is complete. This gives more settling time for the internal SADCs (sub-ADCs) 104 and 112, SDACs (sub-DACs) 106 and 114, and amplifiers, and allows the pipelined converter to operate at a much higher overall sampling rate than a non-pipelined version.
The input to the converter is at T/H 102, the track-and-hold element at the beginning of the pipeline. The track-and-hold is operated at the desired rate for the analog-to-digital conversion. In a conversion cycle the track-and-hold will first sample the signal and then enter into hold mode. In hold mode, SADC 104 converts the track-and-hold output into a digital signal. The digital output is then immediately converted back to analog by SDAC 106. The analog output of SDAC 106 is subtracted from the output of T/H 102. The subtracted output is typically called a residue and represents the error of the first stage of analog-to-digital (A/D) conversion. The error of the first cycle is primarily caused by low resolution of SADC 104 and SDAC 106. The residue is then passed on to the next stage, comprising T/H 110, SADC 112 and SDAC 114, where it is converted in the next conversion clock cycle. In this way the conversion error is reduced in each pipeline stage. The final digital output can be calculated by combining the respective outputs of the various sections, or pipeline stages, with different weighting factors depending on the gains between the different stages.
The achievable resolution is typically limited by the noise performance of the track-and-hold elements. The track-and-hold generally introduces noise by itself. Furthermore, wideband noise beyond half-conversion rate entered into the sample-and-hold is captured by the sample-and-hold and aliased down to base band, (which is the frequency band between DC and half-sampling rate). For example, wideband noise from first stage SDAC 106 would be captured and sampled by second stage T/H 110. In order to minimize noise captured by the track-and-hold (e.g. T/H 110) it would be desirable to limit the bandwidth of the track-and-hold, which would be difficult or even not possible, considering that the required speed of the track-and-hold circuit would lead to the track-and-hold settling between conversion cycles. Hence, it would be desirable to avoid having to use a track-and-hold in each stage and operate the converter in a more efficient mode.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.